1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) of precharge type.
2. Description of the Prior
A bit of memory cell in a dynamic access memory consists of a capacitor for storing image information and a MOS transistor for selecting an address, and a dynamic random access memory includes memory cells arranged around intersections of bit lines and word lines as a matrix. Information of logic "1 "or "0 "can stored according to the amount of charges existing in the capacitor. The information is read by turning on the MOS transistor at a selected address so as to connect the capacitor to bit lines and by sensing a change in the potential between a pair of bit lines.
Recently, a dynamic random access memory is demanded to have a larger memory capacity, so that the size of a memory cell becomes smaller and a larger number of memory cells is connected to bit lines for sensing. Then, a ratio of the capacitance of the capacitor to the stray capacitance of the bit lines becomes very small and this make the change in the potential to be detected very small.
In order to solve this problem, bit lines are divided or a memory array of the memory cells is divided in the direction of bit lines in order to reduce the number of memory cells connected to bit lines to increase a ratio of the capacitance of the capacitor to the stray capacitance of the bit lines to a desired value. Further, in order to prevent the increase in chip area due to peripheral circuits required by the division, a column selection line or a bit line selection signal line is provided by a column address decoder commonly to each of the divided memory arrays.
However, this structure has a problem. That is, a pair of common data lines are connected to a plurality of pairs of bit lines and it is connected to the selected bit lines for reading or writing information. If a common column address decoder provides a data line selection signal to the bit line selection signal line, a pair of bit lines and the common data lines are connected to each other in the non-selected memory arrays via switches for selecting bit lines. Then, the bit lines keep a half precharge level, while the common data lines has a precharge level higher or lower than the precharge level. Thus, the potential level of the bit lines having a small capacitance varies largely; that is, charges are transferred rapidly, the dissipation current increases and the operating potential of the sense amplifier has a worse sensitivity.
In order to solve this problem, in a dynamic random access memory disclosed in U.S. Pat. No. 4,893,277, a pair of common data lines in the non-selected memory arrays are connected to the common source lines of the transistors for amplification of the sense amplifiers, so that the common data lines are kept at the half precharge level about the same as those of the bit lines. The potentials of the common source lines are kept at the half precharge level by a transistor. Then, the above-mentioned difference of the potential between the bit lines and the common data lines vanish, and the rapid transfer of charges does not happen.
However, in the dynamic random access memory, though the potential of the common data lines in the non-selected memory arrays becomes stable at the half precharge level by connecting the common source lines via switches to the common source line of the sense amplifier, the switches for connecting the common data lines to the common source lines are turned off in the selected memory array. Thus, the potential of the common data lines become floating at the half precharge level, and this may prevent stable read operation after the bit lines are connected to the common data lines.
Then, precharge circuits for pull-up are connected to the common data lines in order to solve this problem. However, the precharge circuits increase the layout area.
Even in this high-precharge scheme, however, the sensing action is not stable. Because the precharge level of the common data lines is V.sub.cc, if the bit lines are connected to the common data lines according to a bit line selection signal when the amplification of the sense amplifier is not completed, the potential of the higher potential line of the bit lines is nearly amplified. If the bit lines in such a state are suddenly connected to the common data lines at a higher potential, the bit lines of smaller potential difference are attracted to the common data lines at a higher potential difference. This is liable to affect the following amplification action.
Further, a timing to operate the precharge circuit is a larger problem. In order to operate the precharge circuit after the address selection, if the common data lines located near the bit lines are changed rapidly from the precharge level to the V.sub.cc level at around a timing when the memory cell is read or when the read action is most liable to be affected by noises, noises may be generated.
However, if the timing is delayed in order to solve the problem, a time is not enough for a change in the potential of the common data lines from the half precharge level to V.sub.cc, and the bit lines are connected to the common data lines according to a bit line selection signal at a state wherein the potential is lower than the higher potential line of the bit lines. Thus, both bit lines are attracted to the potential of the common data lines having a rather large stray capacitance than the bit lines, and this may affect the following amplification.